CMOS Inverter Design: Voltage Transfer Characteristics

Lab Assignment 2
CMOS Inverter Design: Voltage Transfer Characteristics
(VTC), Delay, Rise/Fall Time
In this lab assignment, we will investigate CMOS Inverter design and optimization. We will study
impact of transistor sizing on inverter VTC characteristics and rise & fall time characteristics.
Further, delay & rise/fall time dependence on load is analyzed.
1. Design and Simulate a CMOS Inverter:
i. Create a new cell: From Virtuoso command window, click OK→ File → New
Cellview. In the popup window select the name of the library that you created
before (“Sample” in this case), give a name to the component, view name
“schematic” and open with “Schematic L”. Then click OK.
ii. Virtuoso Schematic editor will pop up
Next, add NMOS and PMOS, as well as power and ground nodes to the schematic.
Click on Create →Instance. Add Instance windows opens, click on “Browse” and
the Library Browser window should open.

Make sure to add instances from NCSU_Devices_FreePDK45. On the cell column,
click on NMOS_VTG, and in the view column select symbol. In the Add Instance
window, you can enter the width and length of the transistor (for the NMOS_VTG
set the width to 90.0n and the length to 50.0n). Now put the symbol in the drawings,
then click ESC and use the same procedure to instantiate the PMOS transistor (set
the width to 90.0n and the length to 50.0n). From the Basic library you can get the
symbols for VDD and GND (net names for power and ground nodes).
To correct an error while instantiating a component, click on Edit → and make
required corrections. For instance, rotate or move a component as well as delete it.
The Parameters of the components can also be changed. Select a component in the
drawing and then click on Edit → Properties → Objects. Please make sure to make
appropriate connections for the Bulk of both NMOS and PMOS.
iii. Add instance “vdc” component form the analogLib and in the Add Instance window
use “1” on DC Voltage. Instantiate a voltage generator between the VDD symbol
and the GND symbol, as illustrate in the picture (RED ARROW). From analogLib
choose vpulse and connect it to the input, as illustrate in the picture (WHITE
Click on vpulse:
From the Property Editor:
Voltage 1 =0 V;
Voltage 2= 1 V;
Period = 10n s;
Delay = 0 s;
Fall time = 1p s;
Rise time= 1p s;
Pulse width = 5n s;
iv. Next step is to create wire name: Click on “Create Wire Name”
v. Add Wire Name window will pop up. In the Names section, write input output.
vi. Choose Input wire and click on it. Next, choose the output wire and click on it.
vii. From analogLib, add a Capacitor (C = 10 f) to the schematic as shown below:
viii. Simulation:
Now, we ready to simulate the circuit. To generate the netlist: In the schematic
window click on Check → Current Cell view, there should be no errors, then save.
Click on Launch → ADE L. Cadence Analog Design Environment window will
show up. Follow the steps below to simulate your Cell View Cadence.
a. Click on Setup → Simulator/Directory/Host and select hspiceD as
b. Click on Setup → Model Libraries and insert the library belonging to the
/ home1/fac1/amitrt/Teaching/ECE8893_LAB/FreePDK45/ncsu_ basekit/models/
/ home1/fac1/amitrt/Teaching/ECE8893_LAB/FreePDK45/ncsu_ basekit/models/
Click on Analyses→Choose, Select trans option, and use start (0) and stop (20n)
points. The step (10p) will affect the resolution of your output, so choose it
To select the signals to be plotted: click on Outputs → To be plotted → Select on
Schematic, the go on to your schematic and click on the input and output wires.
Click on Simulation → Netlist and Run. A Waveform viewer will open, so that you
can confront your input and output.
Click on Marker→ Create Marker→ Horizontal : write 0.9 for Y position
Click on Marker→ Create Marker→ Horizontal: write 0.1 for Y position
Question 1: Determine the rise time and fall time of the design
Question 2: Change the width of the PMOS transistor to 160 nm and compute
the rise and fall time.
2. Voltage Transfer Characteristics (VTC):
i. Remove the input vpulse and add “vdc” component from the analogLib. Connect
DC input to the input wire.
ii. Use PMOS width=90n, NMOS width=90n
iii. To do DC Sweep: Click on Analyses → Choose…, then click on the dc box. To
sweep the Gate voltage click on “Select Source” and select the “vdc” connected to
the inverter in the schematic, then use appropriate values for start and stop points.
The step will affect the resolution of your output, so choose it appropriately.
Question 1: Plot the VTC and determine the switching threshold (VSTH) of the inverter.
Question 2: Change the PMOS width to 180nm and NMOS width to 90nm. Plot VTC and
determine VSTH. Give proper substantiation for the VSTH obtained.
Question 3: Change the PMOS width to 90 nm and NMOS to 180nm. Plot VTC and determine
VSTH. Give proper substantiation for the VSTH obtained.
3. Delay, Rise/Fall time:
Remove DC voltage to the input and connect “vpulse” to the input wire.
From the Property Editor:
Voltage 1 = 0 v;
Voltage 2= 1 v;
Period = 10n s;
Delay = 0 s;
Fall time = 1p s;
Rise time= 1p s;
Pulse width = 5n s;
Question 1: Calculate the delay and complete the table below. (PMOS width=
160 nm, NMOS width= 90nm).
Capacitance (C) 10fF 30fF 60fF 100fF
Delay (s)
Question 2: Calculate the rise time and complete the table below (PMOS
width= 160 nm, NMOS width= 90 nm).
Capacitance (C) 10fF 30fF 60fF 100fF
Rise time (s)
Question 3: Calculate the rise time and complete the table below (PMOS
width= 160 nm, NMOS width= 90 nm).
Capacitance (C) 10fF 30fF 60fF 100fF
Fall time (s)
Please plot the waveform for each question.

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